Device profile S-7.A.7 (CTT3) with extended address range A or B
Data width of payload data | |
|---|---|
Cyclic data bits | Acyclic parameter bits |
4 DO | 3 PO |
4 DI | 4 PI |
Cyclic data exchange
The output data bit DO 3 is used for extended addressing A or B.
The cyclic 4 bits of payload output data (DO) according to CTT3 are transmitted with 2 bits of payload data each in 2 cycles and thus with double the cycle time. The 2 bits of payload data in a cycle are consistent with each other. The two packets of payload data bits may be transmitted inconsistently with a maximum time difference of 10 ms. Information regarding the measures for consistent data transmission can be found in the documentation of the respective master.
The input data (DI) is transmitted with 4 bits of payload data per cycle. As a result, all 4 input data bits are transmitted consistently without further influence on the cycle time.
The following tables show how the cyclic data bits of the transmission protocol are used in the profile:
Cyclic output data bits (DO) from the master to the device | ||
|---|---|---|
| DO 2 = 0 | DO 2 = 1 |
DO 0 | Payload data bit DO 0 | Payload data bit DO 2 |
DO 1 | Payload data bit DO 1 | Payload data bit DO 3 |
DO 2 | Multiplexer bit | |
DO 3 | Extended addressing:
| |
Cyclic input data bits (DI) to the master from the device | |
|---|---|
DI 0 | Payload data bit DI 0 |
DI 1 | Payload data bit DI 1 |
DI 2 | Payload data bit DI 2 |
DI 3 | Payload data bit DI 3 |
Acyclic data exchange (parameter bits)
The output data bit PO 3 is used for extended addressing A or B.
Only 3 bits of payload output data (PO) are available for data transmission. All of the payload data is transmitted consistently in an acyclic data exchange.
The output data bit PO 03 is not displayed by the device or in the PLC.
The following tables show how the acyclic output data bits are used in the profile:
Acyclic output data bits (PO) from the master to the device | |
|---|---|
PO 0 | Payload data bit PO 0 |
PO 1 | Payload data bit PO 1 |
PO 2 | Payload data bit PO 2 |
PO 3 | Extended addressing:
|
Acyclic input data bits (PI) to the master from the device | |
|---|---|
PI 0 | Payload data bit PI 0 |
PI 1 | Payload data bit PI 1 |
PI 2 | Payload data bit PI 2 |
PI 3 | Payload data bit PI 3 |
