Device profile S-7.F with standard address range
Data width of payload data | |
|---|---|
Cyclic data bits | Acyclic parameter bits |
4 DO | 4 PO |
4 DI | 4 PI |
Cyclic data exchange
The cyclic data bits DO 0 – DO 4/DI 0 – DI 4 are assigned the respective payload data bits for data transmission. All of the payload data is transmitted consistently without affecting the cycle time.
A standard device with this profile does not support extended addressing with an A address or B address. In an AS-Interface network, in which devices with extended addressing A or B are also connected, the device is addressed in each basic cycle of the A-addressed devices and B-addressed devices. This results in a maximum cycle time of 5 ms for data exchange with this device (see Extended addressing).
The following tables show how the cyclic data bits of the transmission protocol are used in the profile:
Cyclic output data bits (DO) from the master to the device | |
|---|---|
DO 0 | Payload data bit DO 0 |
DO 1 | Payload data bit DO 1 |
DO 2 | Payload data bit DO 2 |
DO 3 | Payload data bit DO 3 |
Cyclic input data bits (DI) to the master from the device | |
|---|---|
DI 0 | Payload data bit DI 0 |
DI 1 | Payload data bit DI 1 |
DI 2 | Payload data bit DI 2 |
DI 3 | Payload data bit DI 3 |
Acyclic data exchange (parameter bits)
The acyclic output data bits PO 0 – PO 4 are assigned the respective payload data bits for data transmission. The bit rate and data consistency are not affected.
The following tables show how the acyclic output data bits are used in the profile:
Acyclic output data bits (PO) from the master to the device | |
|---|---|
PO 0 | Payload data bit PO 0 |
PO 1 | Payload data bit PO 1 |
PO 2 | Payload data bit PO 2 |
PO 3 | Payload data bit PO 3 |
Acyclic input data bits (PI) to the master from the device | |
|---|---|
PI 0 | Payload data bit PI 0 |
PI 1 | Payload data bit PI 1 |
PI 2 | Payload data bit PI 2 |
PI 3 | Payload data bit PI 3 |
