Cyclic data transmission of data bits
The basic cycle of cyclic data transmission for data exchange between the master and the device is approximately 160 µs per device for cyclic 4 bit input payload data and 4 bit output payload data. This results in a cycle time of 5 ms for a maximum of 31 devices. This cycle time increases to up to 10 ms with extended addressing (A/B address range).
Device type | Device profile | Data width of payload data | Maximum cycle times/transmission duration with maximum ms |
|---|---|---|---|
Binary devices | S-7.F | 4 DO | 5 |
4 DI | 5 | ||
A/B device | S-7.A.7 (CTT3) | 4 DO | 20 |
4 DI | 10 | ||
S-7.A.A (CTT3) | 8 DO | 40 | |
8 DI | 40 |
t | Cycle time, [t] = ms |
N | Number of devices |
[1] | Cycle time for the standard address range of up to 31 devices |
[2] | Cycle time for the extended address range of up to 62 devices |
